The present invention relates to switching of plesiochrorous, hierarchical digital traffic signals. The invention also relates to a system for routing plesiochronous traffic signals carrying data on channels at hierarchically different data rate levels in a telecommunications node in a radio network still further the invention relates to a method of switching plesiochrorous, hierarchical digital traffic signals.
There is often a need to be able to switch separate, incoming traffic streams carrying data at different rates, particularly within the area of telecommunications. There is a European Standard for plesiochronous hierarchical traffic named CEPT (Conference of the European Postal and Telecommunication Administration) wherein E1 is the European digital transmission format as deviced by ITU-T (International Telecommunications Union). E1 is a signal format for carrying data at the rate of 2,048 Mbit/s and it can carry 32 channels of 64 kbps each. E2 comprises four multiplexed E1 signals with a data rate of 8,448 Mbps whereas E3 comprises 16 E1 signals with a data rate of 34,368 Mbps. In the North American T-1 format there are hierarchical levels with bit rates from 1,544 Mbps (T1, 3,152 Mbps being the next level etc.) The traffic, i.e. the bit stream has an inherent clock, a so called plesiochronous clock. The clock is therefore neither synchronous nor asynchronous There is often a need to switch separate, incoming streams of several channels carrying signal at a first, for example E1, bit rate as well as several channels with signals of a second bit rate, e.g. E2 signals in a flexible way to form new channels or new signals. Of course the need is the same for the above mentioned T1 and T2 signals or more generally any hierarchically different signals.
As an example, there may be a need to switch four E1 channels to a multiplexer in which they are multiplexed to form one E2 channel. In another example there may be a need to switch one E2 channel to a demultiplexer where it is demultiplexed to form four E1 channels. In yet another example there might be a need to switch three E1 channels to a multiplexer in which they are multiplexed into one E2 channel, the missing fourth E1 channel then being represented by a synthesized channel not carrying any useful information.
The above examples only illustrate some combinations that may be wanted and often there is a need for other combinations of multiplexing and demultiplexing traffic channels of different hierarchical levels.
Since a switching which is as flexible as possible is needed, there has been various attempts to create simple and flexible switching matrixes. One of the most important criteria as far as a switching matrix is concerned, is its ability to leave the multiplexed traffic undistorted. Thus it is especially important that the clock in a plesiochronous bit stream remains unaffected by any switching. This problem is at least two folded. First, due to the fact that the different sit streams may have different paths through the switching matrix, they may be differently delayed in an asynchronous design. This means that the synchronisation between the different bit streams will be last. Second, due to the fact that one bit stream may be represented by two pulses (N-pulse and P-pulse as in the CEPT standard is an example thereon) and the fact that the two pulses may have different paths through the switching matrix, they may be differently delayed and subsequently the inherent plesiochronous clock will be distorted. Numerous attempts have been done to provide a switching matrix handling plesiochronous traffic, either through implementation of asynchronous techniques or through application of synchronous techniques. The design of a large switching matrix using an asynchronous technique involves severe problems due to the manufacturing timing tolerances in used components and tolerances in leap time delay in different conductor paths through the switching matrix. Since there is no way to synchronise such delays in the switching matrix, all the worst case delays will be added to each other. This will demand unreasonably high performances of the individual components and likewise unreasonably exact matching of different conductor paths through the switching matrix. These problems will be even more difficult to handle when the size of the switching matrix increases, i.e. the larger the switching matrix needs to be, the more complex it gets and the problems increase correspondingly. The situation gets even more problematic when the traffic channel goes through a chain of switching matrix units on its way to the target customer interface. Thus it is nearly impossible to build larger and more complicated switching matrixes using an asynchronous technique.
Therefore attempts have been done to use the synchronous technique for the building of switching matrixes. It is known to synchronise all incoming plesiochronous traffic channels by means of buffers before the switching matrix and then recover the original clock again after the switching matrix. In such a manner the switching matrix can be clocked with a clock corresponding to the traffic rate. An example thereon is shown in EP-A-0 226 054. In this disclosure buffers are used for adapting incoming traffic rate to the clock rate of the switching matrix. After the switching matrix buffers are provided for adapting the clock to the outgoing traffic rate. All buffer components are designed for a specific traffic rate. Furthermore there has to be a traffic dependent PLL (Phase Locked Loop) for each traffic rate to recover the original plesiochronous clock. In the system there are a lot of small switching matrixes and buffers, i.e. there are a large amount of components, which makes the system inflexible and invariable
What is needed is therefore a switching arrangement able to handle plesiochronous, hierarchical traffic. Particularly a switching arrangement is needed through which multiplexed traffic will not be distorted. Particularly a switching arrangement is needed through which a plesiochronous bit stream is not affected by the switching. Moreover a switching arrangement is needed through which different bit streams do not get differently delayed through having different paths through the switching arrangement, i.e. that the synchronisation between different bit streams is maintained. Still further an arrangement is needed through which bit streams represented by two different pulses, for example the N-pulse and the P-pulse respectively as in the CEPT standard can be handed in an efficient manner and without their being differently delayed. Further yet an arrangement is needed through which the inherent plesiochronous clock will not be distorted. Furthermore an arrangement is needed which is flexible, simple, and easy to fabricate.
A system comprising a number of switching arrangements and a number of multiplexing/multiplexing means through which the above mentioned objects are achieved is also needed.
Moreover a method of switching plesiochronous, hierarchical traffic signals through which the above mentioned objects are achieved is needed.
Therefore a switching arrangement for switching plesiochrorous, hierarchical digital traffic signals carrying data on channels at different data rates is provided which comprises one synchronous switching matrix with a number of input ports and a number of output ports, each of which input ports being connectable to any one of said output ports. The arrangement further comprises one unitary reference clock with a high frequency for synchronizing and clocking signals such that signals of at least two different hierarchical levels can be switched. According to the invention a high sampling frequency is implemented, e.g. so called xe2x80x9cover-samplingxe2x80x9d. No buffering means are needed on the input side and no recovery means (for recovery of the original clock) are needed on the output side. Particularly the input signals comprise first signals carrying data at approximately 2 Mbps, second signals at a hierarchically higher level carrying data at approximately 8 Mbps. Particularly the first signals comprise so called CEPT E1 signals whereas the second signals comprise CEPT E2 signals. It can also be said that a number of E1 channels and a number of E2 channels are input. Particularly the unitary reference clock has a clocking frequency which is at least as high as 32 times the bit rate of said second signals. i.e. the signals transported with the highest bit rate. Particularly the arrangement also comprises separate asynchronous switching means for switching third signals of a higher hierarchical order than said second signals. Particularly said third signals comprise CEPT E3 signals. In a particular implementation the unitary reference clock has a sampling rate of 270 MHz. In an alternative embodiment the synchronous switching matrix allows for switching of signals of three different hierarchical levels such as E1, E2 and E3 or alternatively T1, T2 and T3. The unitary reference clock then has a sampling rate which considerably exceeds the frequency of the E3 (T3) signals.
Therefore also a system for routing plesiochronous traffic signals carrying data in channels at hierarchically different data rate levels in a telecommunications node in a radio network is provided. It comprises a number of synchronous switching matrixes with a number of non-blocking in-, and output ports for each of which a unitary reference clock is provided which has a high clocking frequency, wherein said switching matrixes route/switch at least first and second signals transporting data at a first and a second bit rate respectively, thus differing one hierarchical level from each other and further a number of multiplexing/demultiplexing means for multiplexing first signals into second signals and/or demultiplexing second signals into first signals in any desirable manner. Particularly, for at least a number of synchronous switching matrixes, asynchronous switching means are provided separately for handling third signals transporting data at a hierarchically higher level than said first and second signals. Particularly, a number of multiplexing/demultiplexing means are further provided for multiplexing/demultiplexing between second and third signals provided. In a particular implementation the first signals are CEPT E1 signals, the second signals are CEPT E2 signals. Even more particularly, in case the switching matrix is clocked with such a high frequency also higher hierarchical signals can be switched, said signals e.g. comprising E3 signals. Alternatively, when separate switching means are provided for higher bit rate signals, said signals comprise E3 signals. In a particular implementation the unitary reference clock(s) has have a clocking frequency of 270 MHz or more. In a particular implementation a processor is provided for handling the settings of at least one synchronous switching matrix and preferably an asynchronous switching means associated therewith to form a switching arrangement. In an alternative implementation there is one processor handling more than one synchronous switching matrix and more than one asynchronous switching means.
Therefore also a method of switching plesiochronous, hierarchical digital traffic signals carrying data on channels at different hierarchical data rate levels is provided. The method comprises the steps of inputting signals of two different hierarchical levels to a synchronous switching matrix using one unitary reference clock with a sampling frequency which considerably exceeds that of the hierarchically highest of said signals, providing other signals of a still higher hierarchical order to a separate asynchronous switching means such that signals of at least the lowest hierarchical orders are switched synchronously whereas signals of higher orders are switched asynchronously. Particularly the method comprises the steps of switching E1/E2 signals synchronously and switching E3 signals asynchronously. Still further the method, advantageously, comprises the step of clocking the input signals to the synchronous switching matrix with a frequency which substantially is 32 times higher than the bit rate of the second level signals, particularly the E2 signals (or T2 signals). Particularly the sampling frequency of the unitary reference clock is 270 MHz or higher. Still further the method includes the steps of multiplexing/demultiplexing signals using multiplexors/demultiplexors which are directly connected to the synchronous switching matrix which is non-blocking, i.e. any input can be connected to any output in any desirable manner.
According to the invention a switching matrix is provided which is able to handle plesiochronous traffic with one unitary system clock and more particularly it can handle both E1 and E2 signals on all traffic paths. According to the invention one unitary system clock with a high frequency is used to synchronize the switching matrix. The clocking frequency is advantageously chosen based on the criteria that the sampling rate of the incoming E1 and E2 traffic must be at least 32 times the highest traffic rate, which is E2. (It is similar for T1 and T2 traffic respectively and the corresponding also holds for other bit rates, generally the two lowest hierarchical orders.) The clock frequency sets the upper limit of the traffic rates possible to apply to a synchronous switching matrix according to the invention. With such a high sampling rate it is possible to keep the jitter and pulse distortion within acceptable limits. The paths through the switching matrix are independent of the traffic rate inserted to it due to the ability of the synchronous system to successively synchronise possible timing distortion. As referred to above, the switching matrix is non-blocking which means that every input port can be connected to any output port without any limitations.
It is an advantage of the present invention that through the inventive concept the implementation problems associated with asynchronous switching matrixes that are built to be traffic independent are avoided, i.e. it is very hard to meet the timing requirements with such asynchronous designs. In addition, it is an advantage of the invention that it is much easier to handle a synchronous design at layout and there will be no long signal paths through the design which are critical in timing and it is also an advantage of the invention that it discloses a straightforward solution as compared to arrangements using rate compensation buffers before a synchronous switching matrix that runs with a system clock on the same rate as the traffic as disclosed in the above mentioned EP-A-0 226 054. Furthermore it is an advantage of the present invention that there is no need to recover a correct clock using PLLs after the switching matrix, i.e. no receiving means are needed as well as no buffering means are needed on the input side.